This invention addresses the issue of reconstructing the timing of a constant frequency digital data channel downstream of its transport on a packet transmission network.
Networks using packet transport divide numerical information to be transported into separate transmission sequences (packets) to which other information fields are added and enable the execution of several functions such as packet routing for instance. The packets containing data on different users are multiplexed with time-sharing techniques to transit on high capacity transmission channels. Transit through switching nodes introduces delays that are typically variable from packet to packet. Packet delay is therefore generally variable according to the specific technique taken into consideration.
These different functional features require mechanisms capable of absorbing the discontinuity of incoming signals to reconstruct their original timing in the network terminal node to be provided.
A solution to this problem is that data incoming discontinuously from packets received are entered in a First-In-First-Out (FIFO) buffer memory. The memory is read at regular time intervals corresponding to the known fixed frequency of original timing ensuring that the memory is prevented from being too full or too empty.
This invention has the object of providing a mechanism based on this basic principle that is capable of operating effectively and securely on a very ample frequency bandwidth without imposing any synchronization constraint on the data channel transported.
A device for reconstructing the timing of a stream of constant frequency data transported on a packet network, and comprising a memory for accumulation of the data 5 of the stream, the memory featuring:
an input whose data are entered as a stream of input data under control of an input timing signal, and
an output starting from which the data are read as a stream of output data under control of a reconstructed timing signal. According to the invention, the device also includes a phase-lock loop that uses the input timing signal and an input signal to be locked to generate a corresponding output signal in lock conditions, the timing reconstructed signal having been obtained starting from the mentioned phase-locked loop output signal. The phase-locked loop can be a digital type lock loop. The phase-locked loop is preferably not provided with ring filters. The phase-locked loop includes as a phase comparator a counter having two increasing count inputs and a decreasing one supplied by the phase lock loop input timing signal and output timing signal. The loop can include means for selective band variation of the transfer function of the phase lock loop. The band variation means can include divisor loops associated to inputs of the counter operating as phase comparator, band variation having been obtained by varying division factor of the divisor loops. The phase-locked loop includes a phase comparator acting on the input timing signal and its corresponding output timing signal to generate a phase deviation signal, and an oscillator loop supplied with the phase deviation signal. The oscillator loop can be a digital oscillator including an accumulator register capable of storing a numerical value given by the sum of its present value and the value of the phase deviation signal. The output signal of the phase lock loop is identified starting from the most significant bit of the accumulator register.
Another divisor can generate the output signal of the phase lock loop by division of the oscillator. Measurement means can be provided for the residual wander present in the reconstructed timing signal, the measurement means being capable of acting on the means for varying the band of the phase transfer function of the phase-locked loop to reduce the band when the level of the residual wander increases beyond a preset threshold.
The residual wander measurement means can calculate the level of the residual wander according to the second derivative of the reconstructed synchronization signal. The residual wander measurement means can include:
counting means to supply subsequent measurements of the same duration as the frequency of the output signal of the period phase lock loop,
comparator means supplied with subsequent values of the duration to generate a comparison value identifying a first order differential value, and
further counting means supplied with the first order differential value and initialized at a given rate, the count value of the further counting means at cancellation identifying a second order differential value indicative of the residual wander.
The residual wander measurement means can have associated to them enabling means sensitive to the average value and the current value of the phase deviation signal, the enabling means enabling operation of the means for varying the phase transfer function band only when the phase deviation signal is equivalent to its average value. Means can be provided to check that the phase-locked loop, has achieved the lock condition to enable operation of the residual wander measurement means only in locked conditions of the phase-locked loop.
The further counting means can be initialized at a rate equivalent to a sub-multiple of the residual wander period with the phase-locked loops in lock conditions. The means for checking achievement of the lock conditions can be sensitive to subsequent values of the phase deviation signal and can identify the existence of the conditions of lock when a certain number (L) of the subsequent values are identical with one another to a certain number (Nx) of the most significant figures.
The subsequent values identical to one another can be identified with a frequency equivalent to the operating frequency of the accumulator register. A process for reconstructing the timing of a stream of input data transported on a packet network by the accumulation of the data of the stream can include:
storing data as a stream of input data under control of an input timing signal, and
reading the stored data as a stream of output data under control of a reconstructed timing signal. The process includes the operation of executing a phase-locked loop using the input timing signal as an input signal to lock and generating a corresponding output signal in lock conditions, the reconstructed timing signal having been obtained starting from the output signal in the lock conditions thus obtained.
The loop lock can be achieved with a digital type phase-locked loop. The loop lock is achieved without ring filtering actions. The loop lock can include a phase comparison step implemented by means of increasing and decreasing counts piloted by the output signal in lock conditions and with the output signal on lock conditions. The process can include the operation of selectively varying the band of the phase transfer function of the phase-locked loop. The band variation is achieved by varying a division ratio for count piloting signals implementing the phase comparison. The phase locked includes operations of implementing a phase comparison between the input timing signal and its corresponding output signal, generating a respective phase variation signal, supplying the phase variation signal to a digital oscillator including of an accumulator register capable of storing a numerical values given by the sum of its present value with the phase variation signal, andxe2x80x9d insert xe2x80x9cThe phase-locked loop includes operations of implementing a phase comparison between the input timing signal and its corresponding output signal, generating a respective phase variation signal, supplying the phase variation signal to a digital oscillator including an accumulator register capable of storing a numerical value given by the sum of its present value with the phase variation signal, and
identifying the output signal in local conditions starting from the most significant bit of the accumulator register. The process also includes the operation of generating the output signal by division of the oscillator output. The process can include the operations of:
measuring residual wander present in reconstructed timing signal, and
varying the transfer function band of the phase-locked loop to reduce the band when the residual wander level is above a preset threshold.
The process can include calculating the residual wander level from the second derivative of the reconstructed signal.